AMD Driver Hints Flagship RDNA 3 GPU Is A Burly Beast With 6 MCDs And A Huge Cache
Let's be frank: it was a pleasant surprise when AMD's Radeon RX 6000-family graphics cards were able to provide solid competition
for (and even outpace, at times) NVIDIA's GeForce RTX 3000 series. The RX Vega series, while competent
, didn't live up to its promise, and the first-generation RDNA-based Radeon cards in the RX 5000 series were a little underwhelming
owing to their midrange focus.
The release of "Big Navi" changed all that, but it's looking like NVIDIA's next generation of GPUs
will be even bigger and more beastly than Ampere despite being named after a high-class lady. According to rumors, AMD plans to respond in kind, with an even bigger Navi GPU that aims to go head to head against Lady Lovelace.
The biggest GPU in the Navi 3x family will probably be known as Navi 31—or rather, probably is already known that way within AMD. Expectations for Navi 31 were extremely high
, but have been tempered slightly with updated information a couple of months ago
. Shortly after that, it came out
that Navi 31 may actually expand the memory bus by 50% compared to Navi 21. That's the GPU used in the RX 6800 and all larger released Radeons.
The latest information seems to confirm that rumor. As part of the very same update to its Linux drivers that we looked at
on Monday, AMD itself has leaked what seems to be the memory configuration of its top-end RDNA 3 GPU, presumably the chip behind the Radeon RX 7900 XT. That configuration: six 64-bit MCDs, each with 32MB of SRAM, for a massive 384-bit memory bus and some 192 MB of Infinity Cache.
If you're wondering what an MCD is, it's a separate die that includes cache, a GDDR6 memory interface, and possibly external I/O for an RDNA 3 GPU. If you've been really out of the loop lately, AMD's confirmed that its next-gen Radeons will be built using chiplets like its Ryzen CPUs.
Many people have envisioned a GPU with multiple chiplets being difficult to build owing to the challenge of splitting up a graphics workload across discrete processors, but it's seeming more likely that AMD will remain using a single GPU compute chiplet with multiple cache, memory, and I/O chiplets. That's a much easier configuration to manage, even if it doesn't give the same benefits for manufacturing as a multi-die GPU.
This information was pointed out by Kepler on Twitter, who also had some interesting observations to make regarding the Infinity Cache allotment on RDNA 3 GPUs. As with RDNA 2, it seems to be approximately 16MB of Infinity Cache per 32-bit memory channel, at least at a maximum. However, Kepler seems to think that AMD is able to double that allotment using 3D V-Cache. By stacking a second 32 MB SRAM die on top of each MCD, the biggest Navi 3x parts could end up with as much as 384 MB of Infinity Cache.
It's amazing to think about a GPU with 384 MB of on-package cache when it wasn't all that long ago
that we were using GPUs with less than 1GB of total VRAM on the board. A massive cache like that should certainly alleviate the performance problems that extant RDNA 2 GPUs suffer when operating in very high resolutions like UHD 4K.