AMD's Zen 4 I/O Die Shot Reveals A Fascinating Ryzen CCD Detail
Thankfully, despite his previous retirement, Locuza (@Locuza_ on Twitter) decided to annotate the detailed photo for us based on his expertise at doing exactly that for many chips in the past. There really aren't many big surprises here; the Zen 4 cIOD includes a single RDNA 2 WGP, just as we knew, and it includes four 40-bit DDR5 memory channels, again, just as we knew. (That's two 32-bit DDR5 data interfaces plus an extra 16 bits for ECC on each motherboard "channel.")
There are a few interesting details, though. First and foremost among them is that the chip really does only have two GMI3 ports. GMI3 is the interface used to connect the CCDs—the Core Complex Dice that host the Zen 4 cores—to the cIOD. That means that you couldn't use the extant cIOD to handle more than two CCDs, contrary to past rumors that AMD was pondering such a processor.
It's also notable that the Zen 4 cIOD really only has 28 PCIe 5 lanes, where previous generations had 32 lanes on-die but only 28 were active. This perhaps speaks to AMD's confidence in the maturity of the 6nm process that the cIODs are fabricated on.
The AMD ISSCC 2023 slide that contained the die shot.
Aside from that, the only other interesting detail is just how much space the graphics hardware takes up on the cIOD. While the single RDNA 2 WGP is quite small, there's still the display control block, the AMD VCN video codec block, and the audio DSP. In total, nearly half of the die is occupied by graphics and audio functions.
With this information at hand, it seems clear that if you want a desktop AMD CPU with more than 16 CPU cores, you're either going to have to snag a Threadripper or EPYC CPU, or simply wait for a later generation when AMD finally bumps the core count per CCD. That may happen with Zen 5, which is rumored to adopt a similar heterogenous processing approach to Intel's 12th- and 13th-generation Core processors.
