Intel Struts New Sapphire Rapids HBM, Rialto Bridge, And Falcon Shores Supercomputing Firepower
While we tend to think "serial code = CPUs" and "parallel code = GPUs", there are some tasks that are best executed on CPUs, yet still need massive amounts of memory bandwidth and big caches, or code that is almost entirely crunchy floating-point compute with minimal I/O. Particularly in the HPC world, you can find a lot of these exotic workloads that simply don't run that well on typical systems owing to their unusual demands.
As evinced by its event at ISC 2022, Intel seems to be seeking to serve these customers with all sorts of customizable super-computing hardware. The company gave the first performance data, vague and relative as it is, for its upcoming Sapphire Rapids-family Xeon Scalable processors with on-package High-Bandwidth Memory (HBM), and it also talked about a couple of upcoming products: Rialto Bridge (the successor to Ponte Vecchio) and the Falcon Shores "XPU".
Sapphire Rapids With HBM For HPC Workloads
First up: the Sapphire Rapids numbers. All of the information that Intel published came in the form of relative comparisons against its current, third-generation Xeon Scalable parts. Overall, it seems like Intel is promising between double and triple the performance from its upcoming HBM-equipped chips compared to the extant models. That's a heck of a lot better than the typical gen-on-gen increases we're used to.
Ponte Vecchio hasn't actually debuted as a commercial product yet, but that may be in part because Intel is shipping every available package it can fabricate to Argonne National Laboratory in Illinois. There, Intel and Cray are building the Aurora supercomputer that Intel promises will surpass the just-launched Frontier machine powered by rival AMD. AMD beat Intel to the punch with the first "exa-scale" machine, so Intel's going to punch back by doubling Frontier's performance.
Rialto Bridge Will Supplant Ponte Vecchio
The successor to Ponte Vecchio will be called Rialto Bridge. Intel divulged little information about the upcoming processors, but there are a few tidbits to take note of. Where Ponte Vecchio tops out at 128 Xe cores, Rialto Bridge will apparently sport up to 160 cores.
That, obviously, means more compute throughput, but Intel is also promising increased memory bandwidth (through "more GT/s", meaning a higher memory clock) as well as "increased I/O bandwidth." Ponte Vecchio already uses PCIe 5.0, and it's fairly unlikely that they're talking about PCIe 6.0. Instead, Intel is probably talking about its own Xe Link interconnect, the analog to NVIDIA's NVLink.
The blue team also notes that Rialto Bridge will bring support for the second revision of the Open Accelerator Module (OAM) socket specification. OAM is part of an attempt (known as OAI) to define a common specification for compute accelerators, including form factor, baseboard, socket, and so on. OAM v2 specifies an increase in power delivery up to 800 watts.
Intel's Powerful Falcon Shores XPU
We've actually already heard about Falcon Shores before, as the company announced it at its winter investor meeting this year. In fact, there's not actually any new information on Falcon Shores in today's presentation, just the same claims that, in comparison to extant parts, it will bring a greater-than-5X improvement in performance-per-watt, compute density, and both memory bandwidth and capacity.
Even for a product that isn't launching until 2024 at the earliest, those are some pretty bold claims, but given Intel's aggressive scheduling for its manufacturing division, they don't sound unrealistic. If Intel can keep up the pace, its competitors could have their work cut out for them.
