SuVolta And Fujitsu Push SRAM Boundaries
Controlling power consumption is the primary limiter of adding features to product types ranging from mobile electronics to tethered servers and networking equipment. The biggest contributor to power consumption is supply voltage. Previously, the power supply voltage of CMOS steadily reduced to approximately 1.0V at the 130nm technology node, but it has not reduced much further as technology has scaled to the 28nm node. To reduce the power supply voltage, one of the biggest obstacles is the minimum operating voltage of embedded SRAM blocks.
By combining SuVolta's Deeply Depleted Channel (DDC) transistor technology – a component of the PowerShrink platform – and Fujitsu Semiconductor's sophisticated process technology, the two companies have verified that a 576Kb SRAM can work well at approximately 0.4V by reducing CMOS transistor threshold voltage (VT) variation to half. This technology matches well with existing infrastructures including existing system-on-chip (SoC) design layouts, existing design schemes such as body bias control, and existing manufacturing tools.
It's all a bit of overkill for most, but Fujitsu Semiconductor is going to advance the technology and aggressively respond to customers' requests for low-power consumption and/or low voltage operation in consumer products, mobile devices and other offerings. The smaller and faster we get, the more mobile our devices can. And who are we to gripe about that?