AMD Ryzen 9 5950X And 5900X Review: Raising The Desktop Performance Bar
Today we get to find out how on-point AMD's messaging was for its Ryzen 5000 unveil. We’ve had the top-end AMD Ryzen 9 5950X 16-core / 32-thread processor and its scaled down, 12-core / 24-thread sibling, the Ryzen 9 5900X, on the test bench for a little while and have our findings laid out for you on the pages ahead. We don’t want to post any spoilers too soon, but suffice it to say you may be itching to upgrade by the time you get to the end of this.
Before we get to the numbers though, we’d like to discuss Zen 3 a bit and explain what makes the Ryzen 5000 series desktop processors tick. First up, the initial line-up and then we’ll dig into the architecture, speeds, and feeds...
Ryzen 5 5600X 6-Core, Ryzen 7 5800X 8-Core, Ryzen 9 5900X 12-Core, Ryzen 9 5950X 16-Core
There are four processors in the initial Ryzen 5000 series lineup, though it’s a safe bet more will be coming later. The entry point is the Ryzen 5 5600X 6-core / 12-thread processor, followed by the 8-core / 16-thread Ryzen 7 5800X, 12-core / 24 thread Ryzen 9 5900X, and the flagship 16-core / 32-thread Ryzen 9 5950X.
The rest of the chips’ specifications look similar to their Ryzen 3000 series counterparts, save for the chiplet configuration, which has significant ramifications on overall latency and performance. Of course, there are additional changes made to the architecture as well, which we’ll get to shortly. However, at a high level, as you go up and down the stack, the Ryzen 5000 and Ryzen 3000 series appear very similar.
Externally, the Ryzen 5000 series also looks similar to previous-gen offerings in terms of their packaging and integrated heat spreader design, and they work in the same socket AM4, for the most part. The vast majority of 500-series chipset-based motherboards have already been updated to support Ryzen 5000 series processors and support will be coming to many 400-series chipsets as well, provided the motherboard has robust enough power delivery. BIOS updates for 400-series chipsets should start arriving in Q1. Support will not be coming to the original 300-series chipsets, however, so early Ryzen adopters will have to spring for a new motherboard as well if they want to upgrade to a Ryzen 5000 series processor.
Major Enhancements To The AMD Zen 3 ArchitectureThough Zen 3 obviously leverages many technologies from earlier architectures, and builds upon the successes of Zen 1 and Zen 2, AMD has made significant changes and enhancements in an effort to lower latency, and boost performance and power efficiency.
Precision Boost 2 returns with Ryzen 5000 series processors. If you recall, PB2 scales frequency and voltage based on the thermal and power headroom available within the chip, socket, and motherboard. Frequencies are adjusted on an approximate 1ms timescale and it’s enabled in the entire range of processors, though the maximum boost frequency and TDP processors is different.
Like all previous-gen Ryzen processors, the Ryzen 5000 series’ voltages will scale up and down based on the workload and environmental conditions as well. For this launch, AMD has provided some detail on what to expect when observing Ryzen 5000 series voltages under a variety of conditions. The scale is rather wide and ranges from .2v to 1.5v, though the highest voltages will only be used for shorter durations during Max Boost periods. The typical peak voltage during sustained, multi-threaded workloads should hover around the 1.35v mark.
AMD also provided some guidance regarding thermals. 65w Ryzen 5000 series processors have a maximum temperature spec of 95°C, while higher-powered chips top out at 90°C. Once those temperatures are exceeded, the processors will self-manage in an effort to bring temperatures down, by either scaling frequencies and voltages, or shutting the system down in extreme situations. In our test environment, using a stock AMD Wraith Prism cooler, with the motherboard and processor installed in a mainstream mid-tower, we observed temperatures at the lower-end of the mid-range scale. These new chips are relatively tame thermally and should be no problem to cool in a properly built system.
While on the subject of power and thermals, AMD also drove home the point that cores in a Ryzen 5000 series processor spend a significant amount of time in a C6 deep sleep state, which is to say the core is completely gated and voltage drops to zero. As such, the average voltage reported by some software may be skewed. In the example given above, over the course of an hour, Core 10 spend 40% of its time in C6. The average voltage was reported as 1.283v, but using the processor’s internal metrics and factoring for the deep sleep state, brings the real weighted average to .77v.
Fabric and memory speeds have also been massaged in the Ryzen 5000 series. The Infinity Fabric, Memory Controller, and Memory Clocks are configured in a 1:1:1 ratio by default. As you push the memory (and fabric and controller) clock up, changing that ratio may be necessary to maintain stability, but overall performance also increases, while latency decreases. With Ryzen 5000 series processors AMD’s claiming that DDR4-4000 memory clocks should be doable while maintaining the 1:1:1 ratio, whereas DDR4-3800 the typical high-point for Ryzen 3000.
There are also some changes coming with the Ryzen Chipset drivers. Provided you’ve got the Windows 10 May 2020 update (or newer) installed on your system, the chipset drivers will now provision the use of the Performance and Energy slider on desktop systems. If users prefer a lower-power or higher-performance state for whatever reason, the slider can be used rather than manually altering the power plan settings.
Digging Deeper Into The Zen 3 Architecture
There are many more internal changes to the chips being introduced with the Zen 3 architecture as well. AMD tweaked virtually every part of Zen 3, from the front-end to the execution units, to the load / store capabilities, and the overall topology and chiplet configurations, which also affect the cache configuration.
In comparison to Zen 2, Zen 3 has a larger L1 branch target buffer and improved bandwidth through multiple parts of the pipeline. The front end is faster to react to mispredictions, latency has been reduced for some operations, and there is additional load/store flexibility. Where Zen 2 could handle 2 load and 1 store per cycle, Zen 3 can handle 3 load and 2 stores. All told, AMD is claiming an average 19% increase in IPC with Zen 3, which is a huge uplift gen-over-gen. Couple that nice IPC uplift, with strong multi-core scaling, and the new unified L3 cache configuration, and Zen 3's performance should look great across a wide variety of workloads.
If we focus on the front-end, Zen 3 has a faster and more accurate branch predictor and it can switch between the op-cache and instruction cache more quickly. Should there be a misprediction, the enhanced front-end is also able to recover faster than Zen 2.
Fetch/Decode in Zen 3 was designed to perform better with “branchy” or largo footprint code, according to AMD. The architecture still uses a TAGE branch prediction unit, but the branch target buffers have been resized (L1=1,024 entries, L2=6.5K entries) and there is a larger Indirect Target Array as well. Along with optimizations to the L1 cache, these changes in Zen 3 result in improved prefetching and better utilization of resources.
The integer and floating-point execution engines in Zen 3 have also been enhanced. Both units are wider, and have larger schedulers, the architecture can perform faster 4-cycle fused multiply–accumulate (FMAC) operations, they have larger execution windows, and new dedicated branch and st-data pickers have been added to the integer unit.
In terms of load/store capabilities, Zen 3 has been enhanced with a larger entry store queue (increased from 48 up to 64), additional TLB walkers (+4) and there is fast copying of short strings, improved prefetching across page boundaries, and better prediction. All told, the load/store enhancements offer higher bandwidth, lower latency, and more flexibility.
And all of the changes in Zen 3 are wrapped up in new die and CCX configuration. Whereas Zen 2 consisted of 8-core dies, with dual 4-core CCX configurations, each with 16MB of L3 cache (for 32MB total), Zen 3 unifies the configuration into a single 8-core complex, with a single 32MB pool of L3 accessible by all cores. This new configuration not only reduces effective overall core-to-core latency, and reduces the need for the CPU to communicate across the IO die, but it effectively doubles the amount of L3 cache accessible to each core.
(Editor's Note: We will be live, November 5 @ 5:30PM EST chatting about the Ryzen 5000 series on our podcast if you'd like to participate in the discussion.)