Intel Unveils Next-Gen Moorestown Atom Platform
Ultra Low Power Characteristics
Let's get down to the nitty-gritty. Like its predecessors, the Atom Z6xx Series is manufactured using an advanced 45nm Hi-K process, but according to Intel, the process has been tweaked and is optimized for SoC processors and now offers the option to use multiple transistor types and higher-voltage IO. Use of this 45nm SoC optimized process reportedly results in a negligible performance loss, but with a positive side-effect of a ~60% reduction in leakage power. The 45nm process used for previous-gen Atom is a 100% single transistor design, which requires low-voltage IO. Intel's Platform Controller Hub MP20 is manufactured using Intel's proven 65nm process.
While the actual execution core in the new Atom Z6xx Series remains largely unchanged from the original--it is still an in-order engine with support for HyperThreading-- Intel has repartitioned the chip to achieve higher performance and lower power consumption. The revamped core is now known as the uLP Atom core (Ultra Low Power). Many of the functional blocks of the older Poulsbo chip have also been integrated into the Atom Z6xx Series SoC along with a number of additional enhancements designed to boost performance and / or reduce power consumption. Additional engineering efforts were made to reduce power consumption of the MP20 Platform Controller Hub and MSIC as well, with the end result being platform that can, in some case, draw as little at 100uW (micro-watts) at idle--not milliwatts, that's micro-watts.
Initially, the Atom Z6xx Series will consist of two parts, a derivative designed for smartphones, with a peak frequency of 1.5GHz and one targeted at Tablets with a peak frequency of 1.9GHz. Additional specifications for the smartphone model include the aforementioned 100 micro-watt idle power (3mW C6 idle), support for single-channel LPDDR1 memory at speeds up to 400MT/s, 24K data cache, 32K instruction ache, 512K L2 cache, HT support, and a 400MHz graphics core clock, with full support for up to 1080P video. The version designed for tablets has all of the features of the smartphone model, but with a 6mW C6 idle power state, and support for DDR2 memory up to 800MT/s. Both chips have a die size of 7.34mm x 8.89m (65.29mm2) and feature a compact 13.8mm x 13.8mm package. We should also note that the smartphone version is designed for ultra-small pocketable form-factors with 3.5” displays that are 11mm thick (give or take), while the Tablet derivative is for slim Tablets less than .5” thick.
As we've mentioned, Intel was able to reduce the total power consumption of the Atom platform through a combination of integration and advanced manufacturing process techniques. But if we dig a little deeper, there are also many new aspects of the Atom Z6xx Series SoC to consider. For example, additional power management improvements were achieved by creating new standby power states subbed S0i1 and S0i3, incorporating an enhanced version of Intel's SpeedStep Technology that throttles CPU and FSB frequencies, and by significantly partitioning the chip and using aggressive gating techniques. In fact, the Z6xx Series SoC has 19 power islands and 12 supply rails, which can all be controlled independently. Basically, if a functional block is not required at any given moment, the SoC has the capability to turn it off.
Every Subsystem in Moorestown has integrated power management capabilities and the devices are actively managed through a combination of hardware, firmware, and software. When devices are idle, they are put into low power states and are only brought out of lower power stats on demand. An integrated power management controller (PMIC) allows for fine grain control of power delivery across the platform and the operating system power management (OSPM) helps to efficiently manage all the hardware's capabilities.
Moorestown's new S0i1 and S0i3 standby power states allow devices based on the platform to remain active and connected while in ultra lower power states. In the S0i1 state power has been measured at 8mW, with and exit latency of 200uSec and an entry latency of 600uSec. S0i3's power has been measured at measured 100uW, with an exit latency of 3100uSec and entry latency of 450uSec (entering the S0i3 state is faster because there's no need to worry about flushing data).
The enhanced SpeedStep capabilities of Moorestown extends CPU frequency scalability to lower clocks and adds support for a new BURST or “Turbo Mode” that can double available bandwidth at higher core frequencies, through a combination of CPU core and front side bus clock manipulation. Whereas the processor core could drop as low as 600MHz on the previous generation, with Moorestown, it can drop down to 200MHz. And the FSB speed can be reduced or increased on demand as well. The hardware dynamically detects the need for higher Bus frequency and makes the switch.
In short, the Moorestown platform features a uLP Atom core and MP20 IO hub that are more highly integrated and consume significantly less power than their predecessors. However, the graphics and video capabilities have been beefed up as well. Although Moorestown features the same graphics IP as Poulsbo/Menlow, which supports OpenGL ES.20, OpenVG 1.0, DirectX 9.L, the frequency of the max frequency on the core has been doubled to 400MHz. Doubling the max frequency obviously results in a significant increase in performance, which gives the platform the capability to smoothly play back HD media at 1080P resolutions.
An Open Peak Tablet Prototype Based On The Moorestown Platform