Intel Demos Transistor Scaling Breakthroughs That Keep Moore's Law Alive And Well
Intel's upcoming RibbonFET technology is set to debut in the company's 20A node next year, but already the chip maker is showcasing the next step: 3D stacked CMOS (complementary metal oxide semiconductor) transistors. Though Intel had filed a patent for such a technology nearly two years ago, it was only in May at ITF World that Intel announced it would be pursuing stacked transistors. At the IEEE International Electron Devices Meeting, Intel demonstrated that the technology works, and it even combined it with its upcoming PowerVia backside power delivery tech too.
While you may have heard of 3D stacking with Intel's Foveros technology, which uses an active silicon interposer to host chips like CPUs and memory within a single package, that's actually on a much bigger scale than what Intel has just demonstrated. It's the individual transistors that Intel has stacked, bringing the density-boosting benefits of stacking inside chips themselves. Increasing density is a key priority for keeping on pace with Moore's Law, which expects transistor count in dense chips to double every two years, allowing newer chips similar in size to old ones to be faster thanks to having more transistors.
While you may have heard of 3D stacking with Intel's Foveros technology, which uses an active silicon interposer to host chips like CPUs and memory within a single package, that's actually on a much bigger scale than what Intel has just demonstrated. It's the individual transistors that Intel has stacked, bringing the density-boosting benefits of stacking inside chips themselves. Increasing density is a key priority for keeping on pace with Moore's Law, which expects transistor count in dense chips to double every two years, allowing newer chips similar in size to old ones to be faster thanks to having more transistors.
The introduction of stacked CMOS transistors represents yet another innovation Intel is adding to its fabrication technology to keep Moore's Law on track. Intel's current-generation Intel 7 process and its upcoming Intel 4 and 3 processes all use FinFETs, which organize the fins of transistors horizontally. RibbonFETs (also known as nanosheets) instead organize those fins vertically for higher frequencies and density, and will debut with the 20A node. These new stacked transistors use a new forksheet design which improves on RibbonFETs and makes stacking possible.
But as Intel's 18A node is confirmed to use RibbonFETs, it means we won't be seeing stacked transistors for some time. Even Intel hasn't put a date on when we will see this technology used in earnest, with the company describing it as a "future" innovation. However, Intel's press release also mentions that the company plans to launch a chip with at least one trillion transistors on a single package by 2030, which implies we'll see 3D stacked CMOS transistors by then. PowerVIA, which was also part of the demonstration, is arriving with the 18A node next year.
