Toshiba Ships Samples Of 3D Flash NAND Capable Of Storing 1TB
Toshiba has just announced that they will begin shipping samples of its 512 Gigabit, three-bits-per-cell, 64-layer 3D NAND (BiCS 3D). Mass production is expected to take place during the second half of 2017.
Western Digital and Toshiba engineers have used digital stacking for their sixty-four layers in order to achieve a much larger storage density for its NAND in a smaller footprint. This technology also enables 1TB chip solutions. The flash memory stacked cell structure is best for applications that require high capacity and performance. According to Toshiba, “realizes a 65 percent larger capacity per unit chip size than the company’s 48-layer, 256Gb (32 gigabyte) device. This increases memory capacity per silicon wafer and leads to a reduction of cost-per-bit.”
Scott Nelson, senior vice president of TAEC’s memory business unit, remarked, “The introduction of our third generation BiCS FLASH coupled with the industry’s largest 1TB chip solution strongly reinforces Toshiba’s flash leadership position. These innovations underline our commitment to developing leading-edge memory solutions, and we will continue to advance our 3D technology to meet the ever-increasing storage market demand.”
Toshiba is reportedly also working on a 1TB product with a 16-die stacked architecture or “the industry’s largest capacity”. Samples of this product are expected to begin shipping out in April. Toshiba has also started constructing its new semiconductor fabrication facility, named Fab 6, and a new memory-focused R&D Center, at Yokkaichi Operations in Mie Prefecture, Japan. The Fab 6 facility will be dedicated to the production of BiCS FLASH.
Samsung started the 3D NAND flash revolution with its 3-bits-per-cell, 32-layer “V-NAND” technology in 2014. Toshiba followed up in 2015 with its 48-layer BiCS 3D NAND. Seagate has even shown off prototype SSDs with a capacity of 60TB due to its use of Micron 3D TLC NAND.
Western Digital and Toshiba engineers have used digital stacking for their sixty-four layers in order to achieve a much larger storage density for its NAND in a smaller footprint. This technology also enables 1TB chip solutions. The flash memory stacked cell structure is best for applications that require high capacity and performance. According to Toshiba, “realizes a 65 percent larger capacity per unit chip size than the company’s 48-layer, 256Gb (32 gigabyte) device. This increases memory capacity per silicon wafer and leads to a reduction of cost-per-bit.”
Scott Nelson, senior vice president of TAEC’s memory business unit, remarked, “The introduction of our third generation BiCS FLASH coupled with the industry’s largest 1TB chip solution strongly reinforces Toshiba’s flash leadership position. These innovations underline our commitment to developing leading-edge memory solutions, and we will continue to advance our 3D technology to meet the ever-increasing storage market demand.”
Toshiba is reportedly also working on a 1TB product with a 16-die stacked architecture or “the industry’s largest capacity”. Samples of this product are expected to begin shipping out in April. Toshiba has also started constructing its new semiconductor fabrication facility, named Fab 6, and a new memory-focused R&D Center, at Yokkaichi Operations in Mie Prefecture, Japan. The Fab 6 facility will be dedicated to the production of BiCS FLASH.
Samsung started the 3D NAND flash revolution with its 3-bits-per-cell, 32-layer “V-NAND” technology in 2014. Toshiba followed up in 2015 with its 48-layer BiCS 3D NAND. Seagate has even shown off prototype SSDs with a capacity of 60TB due to its use of Micron 3D TLC NAND.
